Accurate model for network-on-chip performance evaluation based on timed colored petri net

Keyphrases

• Accurate Model 100%
• Performance Evaluation 100%
• Network on chip 100%
• Timed Colored Petri Nets 100%
• Chip Performance 100%
• Performance Index 22%
• Network Model 11%
• Parallelization 11%
• Communication Difficulties 11%
• High-level Model 11%
• Level of Communication 11%
• Real-time Traffic 11%
• Chip-based 11%
• Router 11%
• Modeling Effort 11%
• Estimation Error 11%
• Service Time 11%
• Buffer Size 11%
• Mesh Network 11%
• Latency Time 11%
• Time Estimation 11%
• Accuracy Analysis 11%
• Architectural Features 11%
• Internal Network 11%
• Traffic Situation 11%
• System-level Model 11%
• Colored Petri Net Model 11%
• Network Latency 11%
• Chip Model 11%
• Synthetic Traffic 11%
• RTL Description 11%
• Latency Measurement 11%
• Equivalent Experiment 11%
• Network Buffer 11%
• Average Latency 11%
• Efficient Network 11%
• Design Steps 11%
• Power Architecture 11%
• Modern Systems 11%
• System-on-chip 11%
• Fast Analysis 11%
• On-chip Evaluation 11%
• VHDL Implementation 11%
• Suitability Model 11%
• On-chip Implementation 11%

Computer Science

• Performance Evaluation 100%
• Model for Network 100%
• Colored Petri Net 100%
• Networks on Chips 100%
• Parallelism 10%
• Estimation Error 10%
• Mesh Network 10%
• Internal Network 10%
• System-on-Chip 10%
• Special Interest 10%
• Network Latency 10%
• Average Latency 10%
• Network on a Chip 10%