An FPGA hardware architecture of Nilsimsa fingerprinting algorithm

Alireza Monemi*, Muhidin Abdullahi Mohamed, Muhammad Nadzir Marsono

*Corresponding author for this work

Research output: Chapter in Book/Published conference outputConference publication

Abstract

Nilsimsa algorithm is a very effective spam fingerprinting technique. This spam fingerprinting algorithm is formulated for software implementation. In this paper, we present an FPGA hardware architecture of the modified form of Nilsimsa algorithm which has similar accurate with the original software-targeted algorithm. The modification results in hardware resources reduction and execution time speed up. The implemented algorithm works at 123 MHz frequency and has a throughput of 1 byte per 2 clock cycles (494 Megabits per second). Our system also needs an extra 512 clock cycles after receiving the entire of the message to compute the Nilsimsa fingerprint. This means the minimum time for computing the fingerprint of a message with the size of 10 Kbytes is 167 μ s, which is equal to 5988 emails per second. For 100 MHz clock, our proposed architecture is 1400 times faster compared to implementation on 32-bit general-purpose embedded processor, and 24 times faster than the implementation on a modern CPU running on 2.64 GHz clock.

Original languageEnglish
Title of host publicationInECCE 2011 - International Conference on Electrical, Control and Computer Engineering
PublisherIEEE
Pages124-129
Number of pages6
ISBN (Print)9781612842288
DOIs
Publication statusPublished - 18 Aug 2011
Event1st International Conference on Electrical, Control and Computer Engineering 2011, InECCE 2011 - Kuantan, Malaysia
Duration: 21 Jun 201122 Jun 2011

Conference

Conference1st International Conference on Electrical, Control and Computer Engineering 2011, InECCE 2011
Country/TerritoryMalaysia
CityKuantan
Period21/06/1122/06/11

Keywords

  • Fingerprinting
  • hardware implementation
  • Nilsimsa
  • spam detection

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