DC-link voltage control strategy for reducing capacitance and total harmonic distortion in single-phase grid-connected photovoltaic inverters

Yihua Hu, Yang Du, Weidong Xiao, Stephen Finney, Wenping Cao

Research output: Contribution to journalArticle

Abstract

High-volume capacitance is required to buffer the power difference between the input and output ports in single-phase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.
Original languageEnglish
Pages (from-to)1386-1393
Number of pages8
JournalIET Power Electronics
Volume8
Issue number8
Early online date14 Apr 2015
DOIs
Publication statusPublished - Aug 2015

Fingerprint

Harmonic distortion
Voltage control
Capacitance
Electric potential
Power quality
Topology
Experiments

Cite this

@article{1a3529758d3d415db09177a374f3a1c0,
title = "DC-link voltage control strategy for reducing capacitance and total harmonic distortion in single-phase grid-connected photovoltaic inverters",
abstract = "High-volume capacitance is required to buffer the power difference between the input and output ports in single-phase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.",
author = "Yihua Hu and Yang Du and Weidong Xiao and Stephen Finney and Wenping Cao",
year = "2015",
month = "8",
doi = "10.1049/iet-pel.2014.0453",
language = "English",
volume = "8",
pages = "1386--1393",
journal = "IET Power Electronics",
issn = "1755-4535",
publisher = "IET",
number = "8",

}

DC-link voltage control strategy for reducing capacitance and total harmonic distortion in single-phase grid-connected photovoltaic inverters. / Hu, Yihua; Du, Yang; Xiao, Weidong; Finney, Stephen; Cao, Wenping.

In: IET Power Electronics, Vol. 8, No. 8, 08.2015, p. 1386-1393.

Research output: Contribution to journalArticle

TY - JOUR

T1 - DC-link voltage control strategy for reducing capacitance and total harmonic distortion in single-phase grid-connected photovoltaic inverters

AU - Hu, Yihua

AU - Du, Yang

AU - Xiao, Weidong

AU - Finney, Stephen

AU - Cao, Wenping

PY - 2015/8

Y1 - 2015/8

N2 - High-volume capacitance is required to buffer the power difference between the input and output ports in single-phase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.

AB - High-volume capacitance is required to buffer the power difference between the input and output ports in single-phase grid-connected photovoltaic inverters, which become an obstacle to high system efficiency and long device lifetime. Furthermore, total harmonic distortion becomes serious when the system runs into low power level. In this study, a comprehensive analysis is introduced for two-stage topology with the consideration of active power, DC-link (DCL) voltage, ripple and capacitance. This study proposed a comprehensive DCL voltage control strategy to minimise the DCL capacitance while maintaining a normal system operation. Furthermore, the proposed control strategy is flexible to be integrated with the pulse-skipping control that significantly improves the power quality at light power conditions. Since the proposed control strategy needs to vary DCL voltage, an active protection scheme is also introduced to prevent any voltage violation across the DCL. The proposed control strategy is evaluated by both simulation and experiments, whose results confirm the system effectiveness.

U2 - 10.1049/iet-pel.2014.0453

DO - 10.1049/iet-pel.2014.0453

M3 - Article

VL - 8

SP - 1386

EP - 1393

JO - IET Power Electronics

JF - IET Power Electronics

SN - 1755-4535

IS - 8

ER -