Time-to-digital converters (TDCs) and time correlated single photon counters (TCSPC) are instruments commonly used in LiDAR systems, quantum optics experiments and many other applications. This work presents a new time-to-digital converter architecture to improve dead time, converter linearity and precision. The priority encoder is a large combinatorial logic circuit and is often the bottleneck in field programmable gate array (FPGA) TDC designs, as the conversion must complete within the TDC's clock period. This work utilizes a new dual clock domain architecture which has allowed for the TDC clock rate to increase by 38.1% from previous work and potentially double for more modern FPGA devices. This reduces the required delay line length and allows for more precise and linear converters as both integral non-linearity and measurement uncertainty scale according to the square root of the number of delay elements used in the delay line. Single shot precision has improved by 12.9% and converter differential non-linearity and integral non-linearity has reduced by 1.27 and 1.57 least significant bits respectively. This work demonstrates a significant improvement to the performance of FPGA based TDCs at the expense of using slightly more block random access memory.
|Journal||Proceedings of SPIE - The International Society for Optical Engineering|
|Publication status||Published - 26 May 2020|
|Event||Advanced Photon Counting Techniques XIV 2020 - None, United States|
Duration: 27 Apr 2020 → 8 May 2020
Bibliographical noteCopyright 2020 SPIE. One print or electronic copy may be made for personal use only. Systematic reproduction, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.
This project has received funding from the ATTRACT project funded by the EC under Grant Agreement 777222.
- Photon counting
- Time correlated single photon counting
- Time-to-digital converters