Implementation of a high speed time resolved error detector utilising a high speed FPGA

John A. O'Dowd*, Vivian M. Bessler, Selwan K. Ibrahim, Anthony J. Walsh, F. H. Peters, B. Corbett, B. Roycroft, P. O. Brien, Andrew D. Ellis

*Corresponding author for this work

Research output: Chapter in Book/Published conference outputConference publication

Abstract

We demonstrate a time-resolved bit error rate detector utilising a field programmable gate array. The proposed detector offers 93 ps resolution operating at 10.7 Gb/s and allows for all the data received to contribute to the measurement allowing low bit error rates to be measured at high speed. Via synchronisation of both the detector and a high speed scope, the bit error rate and the corresponding individual eyes are identified. The operation of the detector is demonstrated by characterising a fast switching tuneable laser.

Original languageEnglish
Title of host publication2011 13th International Conference on Transparent Optical Networks, ICTON 2011
PublisherIEEE
ISBN (Print)9781457708800
DOIs
Publication statusPublished - 7 Nov 2011
Event2011 13th International Conference on Transparent Optical Networks, ICTON 2011 - Stockholm, Sweden
Duration: 26 Jun 201130 Jun 2011

Publication series

NameInternational Conference on Transparent Optical Networks
ISSN (Electronic)2162-7339

Conference

Conference2011 13th International Conference on Transparent Optical Networks, ICTON 2011
CountrySweden
CityStockholm
Period26/06/1130/06/11

Keywords

  • Packet switching
  • Time-resolved error detector
  • Tuneable lasers
  • Wavelength switching

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